Definitions for high-level verification
high-lev·el ver·i·fi·ca·tion

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1. High-level verification

   High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis (HLS or C synthesis), HLV is to HLS as functional verification is to logic synthesis. Electronic digital hardware design has evolved from low level abstraction at gate level to register transfer level (RTL), the abstraction level above RTL is commonly called high-level, ESL, or behavioral/algorithmic level. In high-level synthesis, behavioral/algorithmic designs in ANSI C/C++/SystemC code is synthesized to RTL, which is then synthesized into gate level through logic synthesis. Functional verification is the task to make sure a design at RTL or gate level conforms to a specification. As logic synthesis matures, most functional verification is done at the higher abstraction, i.e. at RTL level, the correctness of logic synthesis tool in the translating process from RTL description to gate netlist is of less concern today. High-level synthesis is still an emerging technology, so High-level verification today has two important areas under development to validate HLS is correct in the translation process, i.e. to validate the design before and after HLS are equivalent, typically through formal methods to verify a design in ANSI C/C++/SystemC code is conforming to a specification, typically through logic simulation.

WikidataRate this definition:0.0 / 0 votes

1. High-level verification

   High-level verification, or electronic system-level verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level abstract level. For high-level synthesis, HLV is to HLS as functional verification is to logic synthesis. Electronic digital hardware design has evolved from low level abstraction at gate level to register transfer level, the abstraction level above RTL is commonly called high-level, ESL, or behavioral/algorithmic level. In high-level synthesis, behavioral/algorithmic designs in ANSI C/C++/SystemC code is synthesized to RTL, which is then synthesized into gate level through logic synthesis. Functional verification is the task to make sure a design at RTL or gate level conforms to a specification. As logic synthesis matures, most functional verification is done at the higher abstraction, i.e. at RTL level, the correctness of logic synthesis tool in the translating process from RTL description to gate netlist is a less concern today. High-level synthesis is still an emerging technology, so High-level verification today has two important areas under development

How to pronounce high-level verification?

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How to say high-level verification in sign language?

Numerology

1. Chaldean Numerology

   The numerical value of high-level verification in Chaldean Numerology is: 8

2. Pythagorean Numerology

   The numerical value of high-level verification in Pythagorean Numerology is: 3

References

1. ^ Wikipedia
   https://en.wikipedia.org/wiki/High-Level_Verification
2. ^ Wikidata
   https://www.wikidata.org/w/index.php?search=high-level verification